Senior Engineer Digital Concept Engineering (f/m/div)

In this role you shape the PORT IP concept and microcontroller architecture within Infineon’s R&D engine. You lead cross-functional effort to define specifications, drive safety and power-efficient digital design, and advance automation of design flows. You’ll collaborate with RTL, firmware, and system teams to translate architectural decisions into robust, scalable IP. The position offers impact on high‑volume digital platforms and opportunities to mentor peers and advance technical standards. You will work in a fast-paced, innovation‑driven environment that values safety, quality, and cross‑team collaboration.

• Lead PORT IP concept development across product families, including feasibility studies and roadmaps
• Shape microcontroller and PORT IP architecture with focus on scalability, power efficiency, and ISO 26262 safety up to ASIL-D
• Steer digital design, verification, and low‑power strategy with robust methodologies and high verification coverage
• Own safe and robust I/O architecture and coordinate digital-analog integration with IP and interconnect teams
• Automate design/engineering processes with Python for flows, data analysis, and auto-generation of registers/docs/verification models
• Manage engineering workflows and cross-functional collaboration using Jira for backlog, milestones, and risk communication
• Act as technical expert and mentor, establishing best practices and guiding engineering direction

• Degree in Electrical Engineering, Computer Science, or related field
• 3–5+ years in digital IC design, concept engineering or related semiconductor roles
• Strong knowledge of Digital Design and Verification (UVM, formal verification); SystemVerilog (and VHDL); familiarity with EDA flows (Synopsys, Cadence, Siemens) and formal tools
• Deep knowledge of Microcontroller Architecture and IP integration; I/O/pad-cell design and pin multiplexing; experience with PORT IP or similar high-volume digital IP platforms
• Proficient in Python scripting for automation; Jira for project management; strong analytical, communication, and proactive mindset
• Working knowledge of functional safety (ISO 26262) and safety-relevant IP design; Nice-to-have: DFT (JTAG/IEEE 1149.1), register-automation (IP-XACT/SystemRDL), Git-based CI/CD, UPF/CPF, CDC/RDC methodology
• Fluent in English; German a plus

• analytical problem-solving
• excellent communication
• proactive mindset
• SystemVerilog
• VHDL
• UVM