Senior Staff Engineer Digital IP (f/m/div)

As a Senior Staff Engineer Digital IP, you shape digital IP solutions across the full design lifecycle, from micro-architecture to RTL release. You develop reusable IP blocks using SystemVerilog/Verilog with standard interfaces, and apply AI-assisted methods to speed up development and improve quality. You will collaborate with Verification, Architecture, Physical Design, Firmware, and System teams, while growing your leadership through design reviews and broader IP ownership. This role combines technical rigor with mentorship in a mission-driven, innovation-focused R&D environment.

• Own full design lifecycle of digital IP from micro-architecture to release
• Develop high-quality SystemVerilog/Verilog IP blocks with interfaces like I2C, UART, SPI, and AHB/APB
• Apply AI-assisted engineering to accelerate development, debugging, and release readiness
• Collaborate with Verification, Architecture, Physical Design, DFX, Firmware, and System teams
• Mentor engineers, lead design reviews, influence architectural decisions, expand IP ownership

• 8+ years of hands-on semiconductor digital IP design and RTL development experience
• Strong SystemVerilog/Verilog RTL coding, design documentation, and RTL release execution
• Experience with automated/configurable RTL development flows and version control
• Scripting or software development experience, especially Python
• Experience or interest in AI-assisted RTL engineering for workflows and quality
• Working knowledge of UNIX/Windows, MS Office, and Git or Perforce

• cross-functional collaboration
• mentoring and leadership
• problem solving and proactive communication
• SystemVerilog/Verilog RTL
• micro-architecture
• RTL development flows