Staff Digital Design Engineer

As Principal Digital Design Engineer, you will shape the digital architecture of power-management ICs and SoCs, leading RTL development and multi-domain integration. You’ll define product roadmaps, mentor technical talent, and drive critical architectures across a new Munich design center. You collaborate with analog, layout, firmware, and verification teams to deliver compact, efficient digital controllers for PMICs and mixed-signal products. This role offers impact on high‑stakes ICs and hands-on leadership in a fast‑moving environment.

• Define top-level digital requirements and develop specifications for digital functions
• Design and integrate digital blocks for PMICs (control loops, state machines, multi-bus systems, clock-trees)
• Develop regulators and timing logic; implement self-calibration and trimming logic
• Support communication interfaces (PMBus, AVSbus, I2C/SPI, PCMI)
• Write synthesizable RTL with reliability and efficiency
• Collaborate with AMS/DV teams to integrate RTL and gate-level netlists in mixed-signal DV environments
• Oversee synthesis, linting, CDC/STA checks, backend/P&R support

• B.S. or M.S. in Electrical or Computer Engineering
• Typically 10-12 years of digital design experience in silicon-proven ICs
• Strong RTL design and FSM/digital architectures for embedded/mixed-signal apps
• Basic understanding of analog and full custom circuit design
• Experience with synthesis tools (Synopsys, Cadence) and flow setup
• Familiarity with RTL simulation, timing constraints, STA, back annotation of parasitics, gate-level simulation, equivalence checking
• Excellent debugging skills and simulation tools (Xcelium)
• Experience with asynchronous digital design and/or embedded cores is a plus

• mentoring and technical leadership
• excellent debugging abilities
• cross-functional collaboration
• RTL design
• finite state machines
• digital architectures for embedded/mixed-signal apps