Staff Analog Design Engineer

In this role you will lead the design of complex analog and mixed-signal ICs, guiding architecture and solving challenging problems. You will mentor engineers, collaborate across functions, and drive successful product delivery for high-density, efficient power management solutions. The position blends hands-on design with leadership to shape IP blocks used in Power ICs across multiple applications. You will work in a startup-like, high-accountability culture in Munich, contributing to cutting-edge PMIC technology.

• Lead feasibility studies for IP macro-block architectures within Power ICs
• Perform hands-on analogue/mixed-signal IP design in planar and FinFET technologies
• Own design verification (pre/post-layout) and documentation
• Provide guidance on IP floorplanning, layout implementation, and parasitic considerations
• Run layout parasitic extraction and post-layout simulations
• Coordinate interfaces with IC design leads and cross-functional teams
• Support silicon lab validation and product characterization tasks
• Mentor junior engineers and manage external contributors as needed

• MS in Electrical Engineering with 5+ years in power IC design or 8–12 years in analogue/mixed-signal IC design
• Expert proficiency with Cadence Virtuoso and simulation
• Strong CMOS analogue/mixed-signal design and layout knowledge
• Experience with parasitic analysis, post-layout simulation, and design-for-manufacturing
• Ability to work independently and in cross-site teams (US and other locations)
• Excellent verbal and written communication skills
• Desirable: lab silicon validation of IPs within PMIC/Power ICs

• ownership and accountability
• cross-functional collaboration
• clear communication
• Cadence Virtuoso
• analogue/mixed-signal IC design
• layout techniques (matching, shielding, routing)