Senior Staff Engineer Design for Test (f/m/div)

In this role you shape the future of silicon by defining advanced DFT and BIST concepts and IPs to maximize test coverage while controlling costs. You lead scan insertion, ATPG, and test-coverage improvements, and support post-silicon deliveries. You’ll drive DFT methodology innovations across Design Enabling and Services, collaborating across chip design, manufacturing, and verification teams while guiding junior engineers. This role offers impact through cross-functional influence and contributions to Infineon’s advanced IC development and manufacturing readiness.

• Define and implement DFT and BIST concepts and IPs to maximize test coverage and minimize costs
• Execute scan insertion and ATPG
• Perform test coverage analysis and improvements
• Verify and support post-silicon deliveries
• Collaborate on DFT methodology innovations and enhancements for Infineon
• Work with chip design, semiconductor manufacturing, and related areas
• Provide technical guidance to DFT engineers, concept engineers, digital designers, physical implementation, and verification teams

• Degree in Microelectronic, Computer Science, Physics or similar
• At least 5 years of experience in Design for Test
• Knowledge of ATPG, test coverage analysis, digital verification; MBIST or LBIST a plus
• Open minded to work with different departments and sites
• Project management experience and methodology development (beneficial)
• Good communication and presentation skills in English; German a plus

• Open minded mentality
• Strong communication and presentation skills
• Cross-functional collaboration
• Design for Test (DFT)
• ATPG
• test coverage analysis