IO / Analog Design Engineer – High Speed Memory Interfaces (m/f/d)

In this role, you will define and own the IO and PHY concepts for high-speed memory interfaces, driving block-level analysis, verification, and silicon bring-up. You’ll translate architectural intent into schematic implementation and work with global teams to ensure seamless system integration. You’ll leverage automation and AI-based tools to enhance modeling workflows and tackle complex IO design challenges. This opportunity lets you shape next-generation memory interfaces within a world‑leading silicon company that values cross-functional collaboration and innovation.

• Define and own IO and PHY concepts for high-speed memory interfaces
• Perform block-level simulation, analysis, and feasibility checks
• Review and guide schematic-level implementation to align with architectural intent
• Support verification, silicon bring-up, and debug activities
• Collaborate with global cross-functional teams to ensure accurate system integration
• Use automation and AI-based tools to improve modeling and analysis workflows

• Minimum 10 years of experience designing mixed-signal IO blocks, including schematic design and simulation
• Proficiency with SPICE or similar circuit simulation tools
• Hands-on experience with Cadence or Synopsys schematic entry environments
• Ability to understand, model, and evaluate block-level behavior
• Experience working in Unix/Linux environments

• cross-functional collaboration
• problem-solving mindset
• technical communication
• mixed-signal IO design
• schematic design and simulation
• block-level modeling