Senior Staff Engineer SOC Implementation (f/m/div)

In this Senior Staff Engineer role, you will shape advanced digital SoC implementations within Infineon’s R&D ecosystem. You’ll translate design goals into robust physical layouts and lead clocking architectures that address deep sub-micron challenges. You work across RTL2GDS stages to ensure timely delivery and reliable timing closure, collaborating with cross-functional teams. This role offers meaningful impact on next-generation SoC designs and opportunities to influence methodologies and flows. You will join a mission-driven team focused on innovative, energy-efficient semiconductor solutions.

• Implement and integrate complex digital SoC designs with focus on physical design (floorplanning, placement, clocktrees, routing, PDN)
• Translate high-level requirements into detailed layout specs using state-of-the-art EDA tools to ensure timing, signal integrity, and sign-off
• Work independently across RTL2GDS flow (synthesis, equivalence checking, physical implementation) for timely delivery
• Develop innovative clocking architectures considering deep sub-micron physical limits and collaborate with cross-functional teams
• Participate in an expert network to drive SoC floorplanning and top-level timing closure and contribute to next-gen designs

• A degree in Electrical Engineering, Microelectronics, or a similar field
• 5+ years in Physical Design handling highly complex SoCs with experience in Synthesis, Place & Route, and Timing Closure; FINFET technologies
• Strong knowledge of Synopsys and Cadence Toolsets in RTL2GDS domain
• Technical leadership in physical design projects
• Programming skills in Tcl, Perl, or Python
• Basic RTL coding
• Understanding of Functional Safety beneficial
• Fluent English; German a plus

• technical leadership
• cross-functional collaboration
• problem-solving
• Synthesis
• Place & Route
• Timing Closure