Staff Engineer Functional Verification & Methodology (f/m/div)

In this Staff Engineer role, you will shape verification strategy for ICs within Infineon’s R&D team, driving advanced verification methods and methodologies. You will work across disciplines to define plans, build verification environments, and implement robust test scenarios using UVM and SystemVerilog. You will influence both digital and mixed-signal verification and contribute to security and safety requirements. This position offers impact through defining verification strategy and mentoring teams while advancing state-of-the-art methods in a global semiconductor leader.

• Create and define verification plans
• Develop the verification environment for ICs using UVM
• Implement test scenarios with SystemVerilog and constrained-random methods
• Develop SystemVerilog assertions for formal verification
• Collaborate with Concept and Application Engineering to shape verification plans and strategies
• Enhance the pool of state-of-the-art verification methods
• Provide proactive support to internal stakeholders of the verification flow environment

• University degree in Electrical Engineering, Computer Science or similar
• At least 3 years of experience in Metric Driven Verification (digital and mixed signal)
• Experience with microcontroller-based ICs and with security and safety requirements
• Excellent know-how with UVM, especially using SystemVerilog
• Experience in technical leadership is a plus
• Knowledge in RTL design and firmware
• Excellent communication skills in English, German is a bonus

• Interdisciplinary collaboration
• Strong communication in English
• Cross-functional teamwork
• Metric Driven Verification (digital and mixed signal)
• UVM (SystemVerilog)
• SystemVerilog